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Lakefield chips will use a new technology called Foveros, which allows different chip components to stack on different layers, and it is because of this feature that Intel has been able to build chips closer and closer.cellphoneThe size of the chip.For Lakefield, the size is close to 12*12 mm.The area of 144 square millimeters is larger than that of the other two.AppleThe company's A12 processor is 83 square millimeters large, but it should be noted that this area contains its memory space, relatively speaking, its circuit board area will be smaller.
Small size is not enough. Lakefield chips are characterized by their low standby power consumption. As a chip for ultra-thin notebook computers rather than mobile phones, they can achieve standby time for devices.Full-day battery standby with very low power consumption (advertised as 0.002W)This is Intel's effort to compete with Qualcomm to bring its mobile chips into the PC market.
Lakefield chips use Foveros logic wafer 3-D stacking technology. Specifically, Lakefield combines a single powerful processor core with a series of smaller, more powerful and energy-efficient kernels. Gomes prefers to call Lakefield chips "big kernels" than the "big and small kernels" combination that ARM promotes for its chips. Combination.
In Lakefield, there is a large core like the latest Ice Lake to perform some performance-intensive tasks, and then there are four smaller Atom Tremont cores to handle tasks such as background processing and less performance-intensive tasks. Take web page loading as an example, when the large core starts to work, the small core group is responsible for the background tasks and other low-performance processes. After the web page is loaded, the activities of the large core will gradually reduce and only the small core will remain in operation.
Intel is testing the Lakefiled prototype, Gomes said, "This is the last stage of preparation for production," and the product will be released by the end of 2019.