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How can China find a breakthrough in the field of open source chips? RISC-V will be a great opportunity

via:雷锋网     time:2019/7/11 14:02:29     readed:105

On June 27th to 29th, hosted by the BenchCouncil, the National Supercomputing Shenzhen Center, Zhongke Shuguang and other units jointly hosted the 6th World Intelligent Computer Conference (BenchCouncil 2019), Bao Yungang researcher is Organized a sub-forum with the theme of “open source chip”, invited Fang Zhixi, chairman of the RISC-V Foundation China Committee, Dai Weimin, chairman of the China RISC-V Industry Alliance, and assistant to the Center for Energy Efficiency Computing and Application, School of Information Science and Technology, Peking University Researcher Luo Guojie, Ph.D. student of the Institute of Computing Technology of the Chinese Academy of Sciences, is a group of experts and scholars. He discusses the current status and future of open source chips represented by RISC-V from various dimensions, and how China can find breakthroughs in the field of open source chips. .

Chairman of the RISC-V Foundation China Committee, formerIntelDr. Fang Zhixi, the vice president, was the first guest to present a speech on the theme “Why is RISC-V a revolution in microprocessors?”Based on the development of microprocessors and some current problems, he explores the advantages of RISC-V and the revolutionary impact on the microprocessor field, and shares his views on the future development of microprocessors. .

Fang Zhixi, Chairman of the China Committee of the RISC-V Foundation

First, Dr. Fang Xixi pointed out that the current state of computing is: 99% of cloud computing is based on the Inter x86 instruction set architecture, 99% of edge computing uses RISC instruction set architecture, and 75% of computing uses ARM (Advanced RISC machines). Microprocessors currently face several major problems, including: First, in the data center, intelligenceMobile phoneAnd the Internet of Things market, the power consumption problem is getting more and more serious. Second, the micro-architecture lacks innovation, performance improvement is not in place, and there is no new idea for decades. Third, security, privacy and reliability are coming in today's microprocessor design. The more important; fourth, microprocessor design relies too much on software ecosystem and software compatibility; fifth, there is currently no microprocessor technology for emerging applications, such as artificial intelligence, big data, cloud computing, and blockchain. .

The emergence of RISC-V has revolutionized the field of microprocessors. As an open source hardware instruction set architecture (ISA), RISC-V, born in UC Berkeley since 2010, is characterized by its simplicity, stability, complete open source and free of charge, while separating the reference and extension instructions. Customized modules and extensions by extending instructions have ushered in a new era in chip design.

Finally, he used Einstein's phrase "Not everything that can be counted counts, and not everything that counts can be counted (not every thing that can be calculated is meaningful; not every piece Meaningful things can be calculated)” expressed his views on the future development of microprocessors. At the same time, he also said that "Future can't be predicted, but it can be created", although it is difficult to "predict" the future of the microprocessor, but we can "create" a better future for the field.

The second appearance was Dr. Dai Weimin, Chairman of the China RISC-V Industry Alliance. His speech was "RISC-V: Historical Opportunities in China's IC Industry."Starting from the development of RISC-V, he shared China's future development opportunities in the field of open source chips.

Dai Weimin, Chairman of China RISC-V Industry Alliance

In the beginning, he pointed out that there is not much room for improvement due to transistors, power consumption, etc., and since 2003 it has switched from a single cancellation processor (chip) to a multi-core high-efficiency processor (chip), which is currently only available on dedicated domain accelerators. Finding a breakthrough is to develop a chip that can perform efficiently on a few specific tasks while improving the power consumption per unit of computing power.

RISC (Reduced Instruction Set Computer) is not only simple 25% in terms of instruction reading, but also has unique advantages in terms of speed and power consumption. The most representative result today is RISC-V. In this regard, Dr. Dai Weimin showed the development of RISC-V (and in China):

  • In 1979, Professor David Patterson of the University of California, Berkeley, proposed the concept of RISC;

  • In 2010, the University of California, Berkeley research team launched the RISC-V instruction set;

  • In 2014, the first edition of the user manual was officially released; in 2015, the RISC-V Foundation was established, attracting more than 150 companies and research institutions from around the world;

  • In 2016, RISC-V became India's de facto national instruction set, and countries such as the United States, Europe and Russia also began to implement nationwide;

  • In 2018, RISC-V was gradually commercialized in China;

  • On September 20, 2018, the China RISC-V Industry Alliance was formally established.

He said that China actually has basically all types of CPUs, but the acumen is still lagging behind, and in order to grasp the initiative of CPU development in the future, it needs to achieve four levels - autonomous, controllable, prosperous and innovative. The characteristics of RISC-V can achieve these four levels, which is in line with the development needs of artificial intelligence heterogeneous computing, and thus provides a rare historical opportunity for China's future development in this field.

In this context, the former China RISC-V Industry Alliance was formally established in October 2018, focusing on more than 100 member units; later, Tsinghua and Berkeley joined hands to establish the RISC-V International Open Source Lab on June 12 ( RISC International Open Source (RIOS) will target the new development direction of the world CPU industry strategy and the industrial innovation needs of Guangdong, Hong Kong and Macau, and focus on the RISC-V open source instruction set CPU research field, and build RISC- with Shenzhen as the root node. V Global innovation network, and ultimately promote the industrialization process and hardware and software ecology of RISC-V technology worldwide.

Then, the panelist of the forum, Professor Bao Yungang, delivered a keynote speech entitled "The Four Steps to Open-Source Chip Ecosystem".Based on his own experience and experience in RISC-V research, he shared his thoughts on open source chips and how to build an open source chip ecosystem.

Bao Yungang, Research Fellow, Institute of Computing Technology, Chinese Academy of Sciences

The researcher Bao Yungang first shared his background in the research field of open source chips: starting in 2012, in order to verify an idea about improving the chip architecture - the tagging architecture, the team started on Sparc T1 I tried it, but I didn't succeed in verifying the idea. After half a year, I finally verified the idea on MicroBlaze after exploration, but I couldn't implement open source and tape-out; I finally turned to RSIC-V and finally launched "Labeled RISC-V." In the process, Bao Yungang has accumulated a lot of experience in the field of open source chips including RISC-V, and there are many thoughts.

He pointed out that for software development, open source can reduce the threshold of innovation on the one hand, and enhance the autonomy and controllability of researchers on the other hand. However, chip development is completely different from software development. It faces a very high development threshold, and only a small number of large companies can afford it, which is a huge obstacle to innovation. It is also worth noting that the open source chip field is now facing a very serious "deadlock" phenomenon: companies are reluctant to invest in open source → can only buy high-priced chips → reduce risk through long-term verification → in turn increase investment → More reluctant to invest. Therefore, reducing the threshold for chip development is of great significance.

And how to reduce the cost? Researcher Bao Yungang pointed out three opportunities: First, Bell's law still exists, and the emerging industry of IOT is emerging, bringing new demands: customization, smaller size, lower power consumption and cost, new Programming mode, while the manufacturing process is more flexible; Second, the end of Moore's Law brings opportunities, chip process costs, especially mature processes are exponentially falling, and the end of Moore's Law also means that the life cycle of mature processes will also Increasingly long, the cost is also declining, bringing great value. Third, the golden age is coming. When open source software, hardware, new languages, new applications and clouds are merged together, many new chemical reactions will occur.

How to develop towards the open source chip ecosystem? In this regard, he believes that there are four steps in this process: the first step is to open source ISA, IP and Soc; the second step is to build the tool chain of language and EDA; the third step is to lower the threshold of verification and simulation; The four steps are software and compilers with adaptations.

“We really need a platform to integrate these features. Our vision is that 90% of the functionality can be achieved through this platform, and only users need to write 10% of the code.”

Dr. Luo Guojie, Assistant Research Fellow, Center for Energy Efficiency Computing and Applications, School of Information Science and Technology, Peking University, presented the theme of "Open Source EDA and Open Source IP: Infrastructure for Future Ecology of Chips"He focused on the relationship between open source EDA and open source IP, the research status of open source EDA tools, and the vision of an open source EDA tool ecosystem.

Luo Guojie, Assistant Researcher, Center for Energy Efficiency Computing and Application, School of Information Science and Technology, Peking University

At the beginning of the speech, Dr. Luo Guojie pointed out that the current chip design is very difficult. The design cost is typical, and the current design cost is more and more difficult to follow Moore's Law, EDA software license, long development cycle, developer's salary, Computing resource overhead and so on have also become important issues in design costs. The complete EDA process of open source chip design involves four aspects: frame design, logic design, physical design and layout design. To achieve success, open source must also balance performance, power consumption and application quality (PPA). Open source is premised.

For the relationship between open source EDA and open source IP, he pointed out that the open source chip consists of four main parts: one is a complete chip, which consists of open source IP; the other is open source IP, which not only requires core, but also ddr phy and usb, Tools such as wifi; third is open source EDA, which not only helps IP design and verification, but also helps IP to achieve integration or chip design; fourth is the open source compiler, RSIC-V is the interface between the compiler and the instruction set.

Among them, Dr. Luo Guojie highlighted the status quo of EDA tools: At present, Cadence, Synopsys and Mentor Graphics, the three major foreign EDA companies, account for 70% of the total annual revenue of the industry in the world, while China has independent EDA software, for example. Huada EDA and EasyEDA products have accumulated many years of technology accumulation and have a large number of successful user cases. However, compared with the three foreign giant EDA companies, there are huge technical differences in the complete automation design process.

As the world's largest consumer market for electronic chips, China's demand for EDA is also the highest in the world. However, under the current EDA situation in China, China's academia and industry can only widely use foreign EDA tools - used annually to buy The use of EDA tools can cost billions of dollars. China's independent open source hardware development EDA tool chain has become an urgent need for development and significant issues.

Not only open source and reliable EDA tools have important significance and research and development motivation for the Chinese market, but the customization of open source EDA tools can also drive the exploration of emerging and emerging technologies in China. At the same time, the challenges facing our country are also very obvious, including chip integration needs to connect algorithms and physical aspects, designing a lot of complex expertise; developing a complete EDA tool chain requires the support and maintenance of many communities; EDA tools running large-scale design Need a lot of high performanceserver.

Finally, Dr. Luo Guojie proposed three steps on how to further enhance the ecosystem of open source EDA tools: First, time-limited back-end integration, solving chip manufacturer interfaces and tools to solve the contradiction between open source EDA and relatively closed-source manufacturing is data; second, from open source hardware From the perspective, support EDA methods for open source IP, and promote the integration of open source IP and EDA communities; third, establish a complete ecosystem of IP+EDA+ development data, and implement tape verification of tools and processes.

At the end of the forum, Yu Zikai, a doctoral student at the Institute of Computing Technology of the Chinese Academy of Sciences, gave a speech entitled "Labeled Development Based on Labeled RISC-V".He introduced the solution to reduce the threshold development - chip agile development, and from the research projects he participated in, shared the advantages of agile development and some experience.

PhD student Yu Zikai, Institute of Computing Technology, Chinese Academy of Sciences

At present, chip development requires considerable manpower and time to carry out, and has certain risks. The threshold for chip development has always been high. In this context, one of the solutions is chip agile development, which can effectively reduce development costs, but also requires three prerequisites: an open instruction set, an open source micro-architecture implementation, and a The design language of the agile development method. The open instruction set RISC-V designed by the University of California at Berkeley, and its open SoC implementation of Rocket Chip project source code, and a hardware construction language for agile development, Chisel, constitute the realization of chip agile development. "The new three carriages."

Dr. Yu Zikai was based on several cases in the development of the “Labeled RISC-V” project by the Institute of Computing Technology of the Chinese Academy of Sciences. He summarized the advantages of agile development and the experience of selecting tools and languages ​​in the process:

  • Compared with traditional development, agile development can achieve an order of magnitude improvement in coding efficiency, while achieving comparable or even better performance, power consumption and area than traditional hardware development models;

  • An open and active instruction set ecosystem (such as RISC-V) and its open source microarchitecture design are necessary to drive innovation in chip development;

  • Chisel's overall signal connectivity, metaprogramming, object-oriented programming, and functional programming can significantly reduce code size and improve code maintainability, but at the same time, Chisel and back-end coordination still have a number of issues to be improved.

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