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NVIDIA said that DNN needs high performance, high precision, and is sensitive to power consumption. It is not easy and costly to build a DNN accelerator. Therefore, it is planned to use low-power, high-bandwidth chip interconnect technology to accelerate multiple inferences. The chips form a mesh mesh network.
Package architecture, chip architecture, PE structure
In a research chip, NVIDIA designed 16 processing elements (PE) for deep learning calculations, with a controller using the RISC-V instruction set, providing 4.01 TOPS (4.01 trillion operations per second) The computing power, supporting up to 36 chips interconnected, the total power of 128TOPS.
When TSMC 16nm process is used, the packaging area of a single chip is 6 square mm (2.4 × 2.5 mm), the core area is 3.1 square mm, and the interconnection of 36 chips is the total packaging area of 216 square mm.Total core area 111.6 square millimeters, still within the controllable range, and counted downEnergy efficiency can reach 1.15TOPS per square millimeter.
However, NVIDIA's research is only a directional exploration, and there will be no corresponding commercial products for the time being, but the ideas may be integrated into future architecture and product design.