Compared with the current DDR4 standard, DDR5 can provide double bandwidth density and higher channel efficiency. The DDR5 standard, originally scheduled to be completed last year, is still in progress, and related products are expected to start appearing at the end of this year.
At Wednesday's International Solid State Circuit Conference, Hailishi Chip Designer Dongkyun Kim presented his first DDR5 chip.
This is a 16 Gb@6.4 Gbps SDRAM with a working voltage of 1.1V. The manufacturing node is 1y nanometer, based on the four metal DRAM process, the encapsulation area is 76.22 square millimeters.
Kim explained some modifications of the delay locking loop in depth.It indicates that Hynix has realized the modification of Delay Lock Loop (DLL) by means of phase rotator and injection lock oscillator.To reduce clock jitter and duty cycle distortion associated with operation at higher clock speeds.
He also described other techniques used by the Hailishi design team, including writing-level training methods to offset clock-domain problems associated with higher speeds, and improved forward feedback equalization (FFE) circuits.
At the same time, Samsung described a 10-nm LDPDDR5 SDRAM. It can achieve a rate of 7.5 Gb/s at a voltage as low as 1.05V.
JEDEC released the LPDDR5 standard earlier this week. The final standard I/O operation rate is 6400 MT/s, which is 50% higher than that of the LPDDR4 era.
As a result, the industry is expected to dramatically improve memory speed and efficiency in smartphones, tablets, and hyperbenchmark applications. In addition, Jim Handy, chief analyst of Objective Analysis, disclosed more technical details about Samsung's new LPDDR5 product.