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Western Data Release Free RISC-V Core SweRV Processor

via:快科技     time:2019/2/17 17:31:41     readed:276

Based on the more open goal of RICS-V, the release of SweRV means that third parties can use it in their own chip design, which can not only promote specific core design, but also promote RISC-V architecture.

The RTL design of the RISC-V SweRV core of Western Data can now be downloaded from GitHub. The design has Apache 2.0 license, which is very relaxed (and non-copyleft), allowing the core to be used free of charge, whether modified or not, and can be released in kind without any modification.

In fact, there are very few requirements for this license, except for appropriate attributes.The only significant limitation is the third party.DevelopmentBusinessmen can't brand their products with Western data.

The SweRV architecture for Western Data is a 32 bit sequential execution architecture with bidirectional superscalar design and 9-level pipeline. It is implemented by 28-nm technology and runs at 1.8 GHz. It can provide 4.9 CoreMark/MHz simulation performance, slightly higher than Arm's Corex A15 architecture.

The core developers plan to use their RISC-V core for embedded design of Western data, such as flash controller and SSD, but it is not clear when it will be put into use.

As one of the main supporters of RISC-V, Western Data believes that third-party use of its core will help promote the adoption of RISC-V architecture by hardware and software designers, which will ensure that the future design of Western Data can be better supported by software developers.

With more and more products released by RISC-V architecture supporters, does this mean that the Open Source Instruction Set Architecture (ISA) can be used as an alternative to ARM and x86 as the main processor?

Rick Merritt, author of eetimes, gives a positive answer and points out the problems RISC-V still needs to solve.

Rick Merritt believes RISCV will be a replacement for Arm and x86 as the main processors, but it will take several years. One problem is that although the ISA has been stable for several months, it has not yet been formally approved. This is the core specification, but some other key specifications may be approved this year. Once the specifications are approved, the RISC-V Foundation will determine the details of compliance testing, through which companies can verify that their products meet the specifications.

Another problem is software. The RISC-V Foundation has just begun to study the Linux startup specification OpenSBI 0.1. Apart from Linux, Android,WindowsThere are no ports for other commercial operating systems.

Jon Masters also noted that operating system ports are only the tip of the software iceberg. Over the past nine years, he has been working on supporting Arm in the Standard Edition.The serverRed Hat Linux. So far, only two commercial systems have been certified to run.

However, RISC-V supporters say that more than 100 organizations behind the growing open source architecture are gradually addressing software issues. At the same time, individual supporters are also making various efforts, including LLVM compilers and more RTOS support, which are expected to be released soon.

So far, in addition to Western data, NVIDIA also plans to use RISC-V controller in its SOC, and Microsemi will use it in the new FPGA. In addition, the startup Abee Semi's RISC-V SoC has received about 20 million orders for smart watches and fitness bracelets.



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