As RISC-V commercials move forward, the industry is full of expectations, but from the instruction set design to the final application, we may have some misunderstandings about RISC-V.
3 months to complete the instruction set design is just a "joke"
RISC-V starts in 2010, when a research team at the University of California at Berkeley was preparing to launch a new project. When the architecture was selected for the new project, the research team saw Arm, MIPS, SPARC, and x86, but these instruction sets were not only More and more complicated, there are still many IP legal issues. So the Berkeley research team temporarily set up a four-person team to develop a three-month summer small project to design a new instruction set, with the goal of a new instruction set that can range from microcontrollers to supercomputers.processor. Specifically, the RISC-V instruction set architecture is simple, completely open source, and free. Separate the base and extension instructions, and customize the modules and extensions by extending the instructions. It should be pointed out that the RISC-V benchmark instructions will not change after the determination, which is an important guarantee for the stability of RISC-V.
Therefore, in the big discussion of China's lack of core, there is a view that Berkeley can design a new set of instructions in three months, which shows that the design of the instruction set is not so difficult. The bigger difficulty lies in the ecological nature of the instruction set. Construction.But in fact, RISC-V officially released the first version of the user manual from 2010 to 2014, and it took four years in the middle. There is one more thing to ignore. Before the RISC-V instruction set architecture, Berkeley already had four generations of RISC instruction set architecture design experience. The first generation RISC instruction set appeared as early as 1981, so the instruction setDevelopmentSimple or not is not so easy to draw conclusions.
Five generations of RISC processors led by Professor David Patterson
As for the ecological construction of RISC-V, established in 2014, Loic Lietar, CEO of GreenWaves Technologies, a French startup that is committed to intelligent edge computing at the edge of the network, accepted his opinion on Lei Feng. He said: RISC-V as a latecomer ecological construction is rapidly developing and is rapidly maturing. Founded by the 2015 RISC-V Foundation, a non-profit organization, more than 150 organizations have joined in two years, including Google.Huawei, Nvidia, Qualcomm, Massachusetts Institute of Technology, Princeton University, Indian Institute of Technology, Institute of Computing, Chinese Academy of Sciences.
GreenWaves Technologies CEO Loic Lietar
RISC-V microprocessor compatibility is not a problem
RISC-V Foundation (RISC-V Foundation)
With the rapid development of the RISC-V ecosystem, many people are concerned about the fragmentation and compatibility issues of RISC-V's openness and scalability. Loic Lietar pointed out: "Compared to mobile phones, PCs, and some high-performance processors, microcontrollers used in sensing devices are less ecologically dependent. From the perspective of GreenWaves, our RISC-V-based 32-bit microcontrollers are mainly oriented to the edge computing needs of the end market such as the Internet of Things. A device will run several applications over a long period of time, not like a mobile phone. It is not the same as installing and uninstalling different applications like a computer, so the degree of dependence on software compatibility is not a problem.At the same time, we embed an extended instruction set based on the RISC-V standard for optimal performance and energy efficiency, which is one of the most different places we have with other competitors. In addition, the ecology of the microcontroller market is mostly open source. Our processors have been transplanted with Arm Mbed OS and FreeRTOS. In the future, we will continue to transplant and adapt to the development needs of terminals in different ecosystems. We have also developed proprietary tools to help software developers automatically generate optimized software code for our 8-core parallel architecture. ”
Loic Lietar gave a negative answer to questions about whether system migration would affect processor performance. He said: "For example, in our GAP8 microcontroller architecture, the operation is generally a simple real-time operating system (RTOS). Because in our application scenario, although the work that the device needs to accomplish is high performance, but from The amount of code and repeatability are relatively simple and do not require complex operating system support. So the impact of various RTOS on performance is not very serious."
In addition to software and OS, the sophistication of EDA tools will also affect the development of RISC-V. Loic Lietar said that no matter what products we have now or our next generation products, the existing EDA tools are enough for us. Development design requirements, and there are currently no problems with special tools that lack RISC-V.
It can be seen that the RISC-V-based microcontroller is not so much ecologically dependent, so what about the higher performance RISC-V processor?
Is RISC-V only the IoT edge processor?
The goal of the RISC-V instruction set design is to meet the needs of processors ranging from microcontrollers to supercomputers, but what we are seeing now is the RISC-V IoT terminal processor. In this regard, Loic Lietar said: "32-bit microcontrollers are technically different from market acceptance in terms of technical difficulty compared to high-performance processors. Starting from 32-bit processors can be seen as a simple to difficult The process, in our participation in the open source project PULP (a laboratory jointly established by the University of Bologna and the Swiss Federal Institute of Technology (ETF Zurich), aimed at researching ultra-low power parallel architecture), too Designed from the most streamlined 32-bit processor, and slowly with a 64-bit processor, you can run Linux.RISC-V has a good foundation to provide 32, 64, 128-bit instruction sets. The instruction set is different from the kernel and has more possibilities, and the RISC-V instruction set architecture can be extended in a standard way for a variety of different applications.”
He also pointed out that the development and landing of RISC-V technology in different markets, from 32-bit processors to 128-bit processors in different scenarios, there is not much technical problem. At this time, the demand from the market will be RISC. The application direction of -V plays a leading role. Nowadays people are more focused on what RISC-V can do now, not what it can do in the future.
According to Lei Feng.com, GreenWaves' general-purpose processor GAP8 is positioned in the long-term battery-dependent edge computing device, which aims to provide ultra-low power consumption for devices working in different scenarios such as smart city, smart home, smart industry and autonomous drone. Edge computing, the ability to intelligent edge computing.
Is RISC-V more suitable for Internet of Things and AI than Arm?
Although asked why Arm will be established at the end of JunewebsiteLoic Lietar said that he was not aware of the costs, ecosystems, fragmentation risks, security and design assurances when attacking RISC-V on the topic of "five things to consider before designing a system chip". The answer to this question is Arm. Perhaps more clearly. But for the question of whether RISC-V is more suitable for Internet of Things and AI, he said: "We have seen the Internet of Things market from the beginning. In 2016, we are considering how to make the Internet of Things richer, not limited to some simple ones. The function of 'rich' represents a richer source of information such as images, sounds, vibrations, etc. How to maintain local processing of such 'rich' information in battery-driven situations (ie ultra-low power edges) Calculation) has become our research and development direction.To meet this need, we need a more targeted architecture to meet this need. RISC-V not only provides us with a large and fast-growing community, but also gives us the opportunity to innovate the architecture to achieve the ultimate in energy efficiency without the need to purchase expensive architectural licenses. This was not possible before RISC-V.”
GreenWaves RISC-V processor-based development board
Therefore, GreenWaves has launched an ultra-low-power application processor for the Internet of Things market, which aims to rely on batteries for long-term complex operations such as pedestrian monitoring, face detection, voice keyword recognition, vibration recognition, etc. Wait. Specifically, GAP8 can use 3.44mW to complete a pedestrian detection, and 0.5mW to complete a face detection. That is to say, relying on a normal battery and working in interval wake-up mode, we can maintain the edge AI work for several years. In terms of performance, in the image recognition algorithm Cifar10 based on CNN image recognition, GAP8 has the energy efficiency advantage of 16 times and 75 times (using hardware accelerator) as compared with STM32H7. And GAP8 as a general-purpose processor can not only run CNN algorithm, but also have more flexibility to perform other types of complex operations on the end side.
Loic Lietar also believes that the Internet of Things has great potential for edge computing, but today's demand is mainly limited by the lack of a processor that can rely on batteries for long-term edge computing. With the birth of products like GAP8, we can find different application scenarios and further expand the IoT market.
Can find a foothold in the competition
Among Arm's five questions for RISC-V, the ecosystem, fragmentation, and design assurance issues have been clearly answered above. The cost and security issues that have not yet been mentioned are actually very clear. Based on the design of open source components, GreenWaves is able to focus resources on its own value-added rather than developing or purchasing core IP, which allows them to significantly reduce costs while developing products while increasing capital efficiency.
In terms of security, Loic Lietar said that GAP8 has all the hardware features that support secure boot and secure execution. In the world of open source software, we have seen that the openness of design has a very positive impact on security because its code can be viewed and tested by a large number of developers and researchers. The market has repeatedly proved that the hidden security design is not really safe.
Finally, when it comes to competition, Loic Lietar said: "We really feel the momentum of the RISC-V market, and we have benefited a lot from it. In the field of artificial intelligence Internet of Things, our energy efficiency is different. In our more than three years of research on edge artificial intelligence, competition has just begun. I believe that every company in the big market of the Internet of Things can find its own foothold.Our products have been launched in February, and many customers are using our development boards. The first production orders will most likely come from China. Of course, in order to stay ahead, our next-generation products are already under development, and it will represent another major step forward in energy efficiency and computing power. ”
Lei Feng Network (Public No.: Lei Feng) believes that the open source of the RISC-V instruction set gives manufacturers around the world a good opportunity to develop the Internet of Things market, and can also achieve the degree of autonomy of the Chinese core to a certain extent, in policies, enterprises, Under the joint promotion of the Institute, RISC-V is growing rapidly, so it is not surprising that Arm feels the pressure, but the IoT market is big enough, both Arm and RISC-V can play their important value. Just in China, which is eager for China's core, the role that RISC-V can play is expected.