The first domestic policy to support RISC-V
According to the "notice", the declaration needs four conditions, including: (1) the declaration unit must be established in the city and have independent capacity for civil liability, the operation state is normal, the credit record is good, the industry development orientation is in line with the construction of the item, and (two) declaration. The content of the project must be within the scope of the project guide; (three) the declarations must seek truth from facts and scientifically and rationally report the relevant economic and technical indicators and the implementation of the funds; (four) the implementation cycle of each project is within two years (2018.7.1-2020.6.30).
Specific to the RISC-V instruction set architectureprocessorThe project guide for the direction of the chip, the annex to the notice, the second batch of Shanghai software and integrated circuit industry development fund (integrated circuit and electronic information manufacturing section) project guide in 2018.
Support the development and industrialization of processor chips based on RISC-V instruction set architecture, 32 bits or more, and the core needs to own independent intellectual property rights.
Direction one: facing the field of Internet of things and industrial control applications, with excellent performance, power consumption, area and other indicators, the priority is to support a project with a clear user cooperation agreement. The cumulative sales revenue during the project execution period is no less than 20 million yuan.
Direction two: in the field of intelligent terminal applications, the main frequency is not less than 1GHz, the performance is not less than 1.5 DMIPS/MHz, supporting dual precision floating point operation, supporting the mainstream operating system, multi-core technology and cache consistency. The cumulative sales revenue during the project execution period is no less than 10 million yuan.
Arm felt pressure
As an important city for the development of domestic integrated circuit industry, the Shanghai government has been actively supporting the development of integrated circuits, which may also be the key to Shanghai's first release of policy support for the development of RISC-V. RISC-V also belongs to the streamlined instruction set. Compared with the Arm instruction set used in current mobile devices, the RISC-V instruction set can be freely used for any purpose, allowing anyone to design, manufacture and sell RISC-V chips and software.
Although not the first open source instruction set, the recent development of RISC-V seems to be putting pressure on Arm. At the end of June, Arm established the riscv-basics.comwebsiteTo attack RISC-V attacks from the aspects of cost, ecosystem, fragmentation risk, security, and design assurance, with the theme "five things to be considered before designing a system chip". But in July 9th, RISC-V also set up arm-basics.com's website to fight back Arm. The next day, in July 10th, Arm closed the attack website, and issued a statement: "we originally built a web page to list the key factors that need to be considered around RISC-V commercialized products to provide information for the intense industry debate. Unfortunately, the result is different from our original intention. This page is different from Arm's collaboration culture, so we have deleted it. In fact, many of our employees also dislike this website. The immediate deletion of this page is because we do not want to give people an impression of open source, because we are also a supporter of many open source communities in many different fields.
Arm and RISC-V are only the epitome of the competition between two streamlined instruction sets, OURS founder and CEO Tan Zhangxi previously said: "IoT applications will be accompanied by new technologies, RISC-V is likely to replace Arm, and of course Arm won't disappear, but it is no doubt that RISC-V becomes a very important player in the IoT market RISC-V." Dr. Tan Zhangxi is a professor of David Patterson from University of California at Berkeley, who is a new Turing Award winner in 2017 and one of the people who raised RISC-V.
The good times of the RISC-V instruction set
Of course, the recognition of RISC-V is closely related to the measured data of the prototype chip. In 2011, the Berkeley research team designed and implemented the 64 bit processor core (named Rocket) based on the sequential execution of the RISC-V instruction set, and carried out 12 flow sheets based on 45nm and 28nm technology. The main frequency of the Rocket chip is greater than 1GHz. Compared with Arm Cortex-A5, the measured performance is 10%, the area efficiency is 49%, and the unit frequency dynamic work is achieved. The consumption is only 43%. These data indicate that the RISC-V Rocket processor core is very competitive. Later, after the Berkeley research team, the open source BOOM Machine (Berkeley Out-of-Order Machine) was introduced to enable RISC-V performance to reach the level of high-end processors in Arm. In 2015, Berkeley research team set up a start-up company, SiFive, to accelerate the commercialization of RISC-V.
Also in 2015, the RISC-V RISC-V foundation was established, attracting hundreds of units in the past two years, including Google, and Foundation.HUAWEIInternational leading enterprises, such as IBM, Mg, NVIDIA, high Qualcomm, Samsung, and Western data, as well as academic institutions such as University of California at Berkeley, Massachusetts Institute of Technology, Princeton University, ETH Zurich, Indian Institutet of Technology, Lorenz National Laboratory, Singaporean Nanyang Technology University, and CAS Computing Institute. Enterprises and research institutes can participate in the evolution of instruction set specification and the development of software and hardware ecosystem through the RISC-V foundation.
Members of the RISC-V Foundation
RISC-V has become a national directives set in India. In 2011, India implemented the processor strategy plan and funded 2-3 projects for developing processors nationwide. Two professors at the Indian Institutet of Technology, Madras, launched a SHAKTI processor project supported by the program to develop a IBM PowerPC compatible processor. For legitimate authorization, the SHAKTI project team and the IBM were negotiating with IBM, but failed to reach agreement. At this point, it happened that RISC-V was successful in the 2013 flow, so the SHAKTI project group gave up PowerPC to embrace RISC-V, and the project target was temporarily adjusted to develop 6 open source processor cores based on RISC-V instruction set. The temporary adjustment was not only criticized but received more support from the India government. In addition, in January 2016, the Advanced Computing Development Center, which had long carried out supercomputer research, was supported by the India Electronic Information Technology Department of 45 million US dollars. The goal was to develop a 2GHz four core processor based on the RISC-V instruction set. In addition, another RISC-V based neuroaccelerator project supported by the India government is also the core of computing. With the projects funded by the government funded by the government of India all close to RISC-V, RISC-V has become the de facto national instruction set in India.
In addition to the India government, the US DARPA and Israel national innovation Bureau, they have also chosen to develop RISC-V based processing platform for national enterprises. Now, the Shanghai municipal government is also the first to support the RISC-V architecture chip, which means that the good era of RISC-V has arrived in China.