According to the relevant regulations of ITRS "international semiconductor technology blueprint", we usually say that 16nm, 14nm, and 10nm are used to describe the node algebra of semiconductor process technology, and that it should be on different semiconductor components, the objects described may be different, for example, in DRAM, it may be described in DRAM Cell. The minimum allowable distance between two metal lines is half the length of the Half-Pitch half length of the Pitch value; while on CPU, it is possible to describe the minimum gate line width in the CPU transistor.
In general, the × × nm process describes the accuracy of the process in place of the machining scale, but it does not refer to the characteristic size of a specific structure in the semiconductor device, but to the minimum of the size of the machining accuracy. Here we mainly discuss the process of CPU, because the process plays an important role in CPU performance, power consumption, heating, and the effect of process change on CPU performance is very great. Previously we also mentioned that 14 nm is usually used to describe the gate width of the transistor.
Why do we use gate width instead of other linewidth to characterize process nodes?
This is mainly concerned with the problem of transistor structure. In general, the CPU internal logic gate circuit uses MosFET, which has three electrodes, a gate (Gate), a source (Source), and a drain (Drain), in which the voltage difference between the gate and the source can control the current from the source to the drain. Control function.
At the same time, such characteristics as the electron mobility of transistors are dependent on the doping ions and the production process, basically it is impossible to move, but the ratio of the length to width of the gate of the transistor can be done. In the case of the same voltage, the smaller the gate width, the electrons may be from the negative pole to the crystal substrate. Positive current flow causes leakage, and leakage current will bring rise of static power consumption.
So grid line width is very important. Gate line width is usually considered the most important parameter in the design of large scale integrated circuit, so it is used as the node of the semiconductor process. This is the standard of the traditional process process.
So the meaning is that the smaller the process is, the better?
That's true, you think, the smaller the line width, the smaller the size of a single transistor, the smaller the size of the CPU die that is made, the more CPU die can be produced with the same piece of wafer, and the invisible will increase the manufacturer's income (the more pieces). Conversely, you can integrate more transistors in the same die area, and CPU performance will also be improved (of course, this is not absolute).
Secondly, because the gate width becomes smaller, the working voltage will reduce the power consumption of CPU accordingly, and in more advanced technology, the transistor cutoff frequency will have better performance and CPU will work at higher frequency. So we often see SoC CPU say, we use more advanced 10 nm, power consumption drops × × 10, frequency increases × ×, performance improves × × 10.
TSMC's 10nm has been mass-produced for a long time, but Intel has not shipped yet, and Intel's invincible technology has failed?
A few years ago, when Intel went from 22nm to 14nm, everyone was saying that Intel was at least 3 to 5 years ahead of other countries in the process of manufacturing, but it didn't look good, but they found that Intel 14nm had been polished over and over again. From Skylakeo 14nm to Kaby Lake(14nm Lake(14nm, it has been used for three generations, and is said to have 14nm, which was originally said to have had a lot of technical problems.
In contrast to the rival TSG, Samsung in the process of generation, 16/14nm nodes catch up with the progress of Intel, it is surprising that TSI, Samsung's 10nm process is far earlier than Intel, related products (such as high pass 835) even sold in the market for a whole year, tcht even produced 7n in this year. M chip, what's the matter again?
The general public thinks that 10nm is definitely better than 14nm at 12 nm and better than 14nm. Just when Intel is about to be drowned out by negative public opinion, it has broken the "mystery" behind the number of nanocrystalline processes, because TSMC. Samsung's craft numbers have all gone through varying degrees of "beautification," clever nomenclature, or "digital" suppression, even though Intel lost on "numbers." But Intel is superior in terms of key technical parameters at all levels of the process. This was the case with 14nm before, when the × × nm process began to move away from its original scope, and people began to "fake."
In the 14nm era, Intel has already kicked off a secret behind the scenes.
Techinsights also made a comparison. Intel 14nm is better than Samsung's 14nm LPE.
Intel indicates that line width represents only process nodes, but to measure the quality of this process, the parameters of Gate Pitch grid spacing, Fin Pitc fin spacing, Fin Pitch minimum metal spacing and Logic Cell Height logic unit height parameters are more useful for reference. At the same time, the Intel processor architecture and integration department head, the senior academician Mark Bohr proposed the Transistor Density transistor density to measure the semiconductor technology level, and proposed the following formula:
For example, last September, on the Technology and Manufacturing Day held by Intel, three 10nm technology related technical parameters were announced, and we saw Intel on these key technical indicators, the fins produced by the 10nm lithography, such as Intel's 10nm lithography, were smaller (attention to Intel male). Cloth is the contrast of the interval, not the width of the line, more meaningful. As a result, the transistor density is almost two times that of TSG and Samsung, reaching 100 million transistors per square millimeter, while maintaining a fine tradition of low logic unit, which has more advantages over the 3D stack.
Semiwiki recently reported on the density of transistors in Samsung's 10nm, 8nm and 7Nm processes. The transistor density of the 10/8/7nm process is 55.10/64.4/101.23 MTr/mm2, respectively. It can be seen that Samsung's 7Nm technology only manages to catch up with Intel's 10nm on the transistor density. Who's playing tricks?
Where is the limit of the process?
When the process is lower than 20nm, because the silicon dioxide insulating layer is too thin, only a few atoms are so thick, then this time is very unstable for the transistor, which will lead to the leakage of the electrons at random through the barrier and increase the power consumption of the chip. However, this is a small problem. Intel has made the high dielectric constant film and metal gate integrated circuit, and the familiar FinFET fin type field effect transistor structure. By increasing the insulation layer surface area to increase the capacitance value, to reduce the leakage current problem. At the same time, in order to produce 7Nm line width, the consensus of the industry is the use of EUV ultra violet as the photolithography light source, with less exposure times and not to overcome the diffractive effect of optical proximity correction, but there are still a lot of problems, so EUV lithography is not fully mature.
When the process progressed to 7Nm, the semiconductor industry was more indifferent because on the silicon based semiconductor, the line width of the transistor dropped to 7Nm, an inevitable problem, the famous quantum tunneling effect.
In classical physics, when the energy of a macro particle is less than the barrier height, it is impossible for the particle to pass through the barrier, but for the microscopic particles, with the two iconicity of the wave particle, the magic quantum effect appears, even if the energy is lower than the barrier height, there is still a certain probability to break through the potential barrier. This will cause a big problem, the electron in the past is not, monitoring is not, the logic gate should output 0 or 1, the answer does not know, then CPU can not work normally, so to stop the problem.
Intel, TCHC, Samsung and other semiconductor manufacturing frontiers have studied this problem, and there are still some measures to prevent the quantum tunneling effect. For silicon based semiconductors, Intel is expected to be 5nm or 3nm; Samsung's words will follow the 8/7/6/5/4nm LPP process, and 4nm will introduce the Multi Bridge Channel FET structure (MBCFET, multichannel field effect tubes), the unique GAAFET (logical door loop field effect transistor) technology, and the use of two-dimensional nanoscale Physical extension and the limitations of FinFET architecture.
The media on the 3nm process are not based on silicon oxide, but a new type of composite semiconductor materials such as graphene, and all are laboratory breakthroughs that can not be produced in a short period of time. But finding new materials instead of silicon to make transistors with lower production is an effective solution.
The virtual reality behind the nano process technology
Read the full text, you know that the current semiconductor process of the so-called 10nm, 7Nm has deviated from the original category, no longer a strict sense of line width, 16nm "optimization" can be called 12NM, 10nm "optimization" can also be called 8nm. Intel, as the advocate of Moore's law, is naturally angry, but criticized the Samsung and TSMC's "digital beautification" for several times. In fact, from the transistor density parameter, Samsung's 7Nm Intel 10nm, so it seems that Intel's 10nm dystocia is also reasonable, the target is too high, but is cunningly changed a name to win by the friends, but the Volkswagen, but because they do not understand the process of virtual reality and believe in the manufacturer's word. Intel's manufacturing technology is not that bad, and is still in the leading position in the world.